About Me
Hello! My name is Maddie Masiello, and I am a 4th year electrical engineering student at Cal Poly SLO, originally from Littleton, Colorado. I have extensive hands-on experience in PCB design, circuit analysis, and hardware debugging, specializing in Altium, circuit design, and system integration. Proven track record of designing complex electrical systems, optimizing production processes, and resolving critical hardware issues. Skilled in managing technical projects, collaborating across teams, and delivering innovative solutions for real-world challenges. Strong foundation in circuit theory, power systems, and micro-controller programming, ready to contribute effectively to advanced engineering projects. Outside of my studies, I enjoy skiing, playing ice hockey, biking, and playing viola and piano.
Work Experience
Edge Autonomy
Electrical Production Test Intern (June 2024 - September 2024)
San Luis Obispo, CAI had a second internship at Edge Autonomy where I...
- Designed multiple PCBs from initial schematic generation to final production using Altium.
- Used circuit analysis techniques to construct circuit boards used for testing parts in production.
- Integrated ESD protection into PCB designs, developed USB-C power delivery systems, integrating IC controllers for voltage/current regulation onto board.
- Contributed 8 complex Altium footprints/3D models to workspace
- Utilized SolidWorks to create fixtures for PCB testing and assembly.
altium
usb-c
esd
3d modeling
pcb design
pcb testing
solidworks
Edge Autonomy
Electrical Engineer Intern (June 2023 - September 2023)
San Luis Obispo, CAIn my first internship with Edge Autonomy, I...
- Diagnosed and resolved issues with overheating PCBs, including component replacement and validation.
- Initiated the assembly of a ground-based test rig for aircraft system integration.
- Conducted root-cause analysis on faulty batteries and helped implement corrective measures.
- Drafted and executed testing procedures for coaxial cables using a spectrum analyzer.
- Played a key role in resolving non-conformance issues related to air data pods.
- Gained experience with JIRA for tracking project progress and managing tasks within a team.
pcb design
pcb validation
analysis
jira
Projects
DSP Guitar Delay Pedal - "Repeat-inator"
The “Repeat-inator” is a custom-designed guitar effects pedal that applies a digital delay to an incoming audio signal. When a guitar is plugged into the input, the analog signal is converted into digital form by the STM32’s built-in ADC, stored temporarily using a circular buffer, and then played back after a delay period via an external DAC. This creates an echo-like repetition of the original sound. Users can adjust the delay time, the amount of feedback (how many times the sound repeats), and the dry/wet mix (balance between original and delayed signals) using potentiometers. These parameters are read in real-time and affect the behavior of the audio output dynamically. The system also features a true bypass button that lets users completely skip the delay effect, passing the guitar signal directly from input to output. The device is optimized for low latency and high-fidelity audio performance, tailored specifically for live or studio guitar use.
Binary LED Counter and Instruction Timer using STM32L4A6ZG Nucleo Board
This project implements a 4-bit binary LED counter and an instruction execution timing measurement system using the STM32L4A6ZG microcontroller. The LED counter counts from 0 to 15 with a visible delay, and the oscilloscope was used to calibrate and measure the delay loop. Execution timing was measured for a range of data types and arithmetic operations, and results are summarized. All Source code and data can be found in the project document 
Keypad Interface - STM32L4A6ZG Nucleo Board
This design project implemented a keypad interface using the STM32L4 microcontroller. A 3x4 matrix keypad was connected to GPIO pins, and software was developed to detect and identify keypresses through polling. The keypad module was designed to include proper configuration, keypress detection, and software debounce functionality. Upon detecting a valid keypress, a corresponding 4-bit binary value was displayed using four LEDs 
Digital Countdown Timer Game - STM32L4A6ZG Nucleo Board
This project implements a digital countdown timer using an STM32 microcontroller, a keypad for time input, an LCD for display, and LEDs for visual feedback. Users input the countdown time in MM:SS format using the keypad, with digits entered from right to left. Once the timer starts, the LED flashes once per second during the countdown, and performs a "dance" sequence when the timer reaches zero. The system features multiple functional states, including a greeting screen, time input mode, active countdown, and completion state. Although the behavior of the star/reset button can vary depending on how quickly it is pressed, the system performs reliably. Additional attention was given to minimizing delay functions to improve response time, and throughout development, the importance of precise timing - especially when working with the LCD - was a key takeaway. Design details can be found in "Countdown Timer Project Report" above.
Digital Reaction Timer Game - STM32L4A6ZG Nucleo Board
This project features a reaction timer game built on the STM32L4 microcontroller. The system uses a 16x2 LCD and onboard button/LED to measure user reaction time with 1ms accuracy. After the user initiates the game, a randomized delay triggers an LED signal, prompting the user to respond as quickly as possible. The LCD displays the reaction time, and the system automatically resets for the next round. The project features an interrupt-driven state machine, hardware RNG, and clean modular design for responsive and accurate timing. Project source code and design details can be found in the "Countdown Timer Project Report" above.
Pipelined RISC-V CPU - Data Forwarding, Hazard Detection, and Control Handling
This project was implemented in CPE 333 (Computer Hardware Architecture and Design) at Cal Poly, and is a 5-stage pipelined OTTER RISC-V CPU with dynamic hazard handling, including full support for data forwarding, stall logic for load-use hazards, and flushing on control mispredictions.Our group began by implementing two hazard multiplexers (HazardMuxA and HazardMuxB) in the execute stage, enabling operand forwarding to avoid incorrect computation due to RAW (Read After Write) hazards. The hazard unit detects when forwarding is needed by comparing source and destination registers across pipeline stages and checking the write-enable signal. It selects the correct forwarded data from either the MEM or WB stage when needed. If no hazard is detected, values pass through normally. The load-use hazard is separately detected when a load instruction is followed by a dependent instruction; in this case, the pipeline stalls the PC and decode stage and flushes the execute stage. For control hazards, we implemented a static branch-not-taken predictor. However, the predictor initially failed due to incorrect PC selection logic being placed in the decode stage instead of the execute stage where the branch condition is actually resolved. After correcting this, we added logic to compute actual_pc_selE in the execute stage based on whether the instruction is a branch, JAL, or JALR and if the branch was taken. Flush logic ensures misfetched instructions are removed from the pipeline and replaced with the correct ones. We verified our implementation with waveform analysis, which confirmed that: Forwarding paths correctly deliver the necessary data in the EX stage, Load-use hazards insert the correct number of stalls, Control mispredictions trigger appropriate flushes and PC redirection. Lastly, we compared the performance of our pipelined design to our earlier multi-cycle implementation. The pipelined CPU completed a 50x50 matrix multiplication benchmark over one million times faster and consumed a total of 93 mW on-chip power, while maintaining similar resource utilization.
Direct-Mapped L1 Instruction Cache for Pipelined OTTER MCU
This project was implemented in CPE 333 (Computer Hardware Architecture and Design) at Cal Poly, and is a direct-mapped Level-1 (L1) instruction cache, designed to improve the efficiency of instruction fetching in our pipelined OTTER RISC-V CPU. The cache consists of 16 blocks, each holding 8 instructions (words), and operates using simple hit/miss logic based on a tag and valid bit array. We started with the provided template and modified the cache module to properly track and compare tags. We added the critical line tags[index] <= pc_tag; to correctly update the caches tag array during block replacements—ensuring proper hit detection. When a hit occurs, the corresponding word is fetched from the cache; otherwise, on a miss, a NOP (0x13) is issued while the block is fetched from instruction memory. We also implemented a finite state machine (FSM) with two states: ST_READ_CACHE (normal operation) and ST_READ_MEM (cache miss handling). When a miss is detected, the FSM transitions to ST_READ_MEM, stalls the PC, and signals the cache to load a new block. Once loaded, the FSM returns to ST_READ_CACHE, and the pipeline resumes with the correct instruction. To integrate the cache with our existing pipelined OTTER MCU, we modified the instruction fetch and PC update logic. Specifically: We gated the IF/ID register and PC updates using both hazard stall signals (StallD, StallF) and the new Cache_stall signal to prevent premature instruction fetching during a miss. We ensured that the cache data and FSM outputs aligned with our existing pipeline stages, correctly substituting a NOP when stalling and resuming normal fetches post-update. Source code and design details can be found in the report.
Digital-to-analog converter (DAC) using the SPI (STM32L4 MCU & MCP4821 DAC)
This project demonstrates the integration of an STM32L4 microcontroller with an MCP4821 digital-to-analog converter (DAC) using the SPI communication protocol. A 4x3 matrix keypad is used as user input to enter a 3-digit voltage value, which is then converted into a 12-bit DAC word and transmitted to the MCP4821. The system enables real-time voltage output from 0.00 V to 3.30 V, with input validation, output capping, and reset functionality. The implementation was verified using a logic analyzer and calibrated to meet specified accuracy requirements.
UART Video Game - Treasure Hunt
This project explored UART communication using the alternate functions of GPIO pins on an embedded system. The goal was to enable communication between a microcontroller and a terminal, such as one on a laptop. To demonstrate this functionality, I created a simple game where a player character can move around and collect treasures. The project includes a fully operational terminal interface and allows the user to go through both the initial stage in which characters are echoed back to the terminal, and the game stage. In the game stage, the borders all are functional allow the character to wrap around to the other side of the screen when crossing. More features include multicolor player character, treasure that turns the character red for 3 turns and solid borders. The player character was turned from a single character into characters resembling a stick figure. The treasure functions by activating when the center of the player character is over the treasure, then for the next three moves the character will be red. There are no known bugs in the design. An important lesson learned was how to use the UART interface and properly formatting in the terminal with escape codes as it is very common in embedded systems for debugging and communicating with computers. 
Circuits Lab Rube Goldberg Machine
This project was created during my Circuits II lab at Cal Poly. Each week, we designed and implemented a different segment of the circuit, building the project step by step. Each segment represents a different part of the circuit, as shown in the block diagram. We showcased our final design at the end of the quarter. Encouraged to be inventive, we designed a Rube Goldberg-style machine, triggered by a user entering a "passcode" by playing a combination of pitches on a capacitive touch piano. The sequence ends with an LCD display, serving as a creative alarm system.
Digital Logic Interfacing Project
This project was created in EE 307 / EE 347 Lab (Semiconductor Device Electronics) at Cal Poly. My group and I designed a custom interface for our designed circuits. Throughout the quarter, we analyzed, designed, and constructed digital logic gates, focusing on Positive Emitter-Coupled Logic (PECL), Transistor-Transistor Logic (TTL), and Complementary Metal-Oxide-Semiconductor (CMOS) technologies. The project involved building a PECL OR-NOR gate, interfacing TTL to PECL, and further integrating the PECL with the CMOS.
Pendubot PID Controller Design
This project was created in EE 302/EE 342 (Classical Control Systems) at Cal Poly. The Pendubot system consists of a motor, a pendulum arm, and sensors that measure the angles of both the rotor and the pendulum arm. By controlling the motor, the goal is to stabilize the pendulum in either the suspended or inverted position. My lab group:- focused on the behavior of second-order systems by deriving transfer functions and analyzing the effects of poles and zeros on system responses,
- designed a single-input single-output (SISO) controller for the Pendulum angle,
- focused on the application of Root Locus methods to improve transient response behavior,
- designed and implemented a lead compensator to improve transient response, increase stability margins, and enhance overall system performance,
- designed a PID controller that effectively minimizes steady-state error while meeting transient response specifications,
- used two different tuning methods, Manuel and Ziegler-Nichols, to adjust the PID gains (Kp, Ki, and Kd) through simulations and hardware experiments
- utilized frequency response design methods to look at gain and phase margins to help us understand the stability of our system.
Matrix Multiplication in RISC-V Assembly Project
This project was implemented in CPE 333 (Computer Hardware Architecture and Design) at Cal Poly, and is a matrix-matrix multiplication algorithm entirely in RISC-V assembly language. The primary goal was to deepen our understanding of low-level programming, stack operations, and the RISC-V calling convention while applying a fundamental linear algebra operation used widely in engineering and computer science. We wrote an assembly routine to multiply two square matrices (e.g., 3x3 up to 50x50), following the standard algorithm: multiplying each row of matrix A with each column of matrix B and summing the products to compute the resulting matrix C. This was done using nested loops and careful management of memory through the stack.After implementing the algorithm, we verified the output by comparing our results to those generated by an online matrix calculator, ensuring correctness with automated diff checks. This project reinforced key concepts in assembly programming and algorithm implementation and provided hands-on experience with mathematical computation at the instruction level.
RISC-V MCU
This project was completed each week throughout CPE 233: Computer Design & Assembly Language Programming. Using previous knowledge and experience with digital logic & FSMs, I designed a basic CPU through Vivado for simulations & testing, using Assembly to represent the CPU on a Basys3 Board.Education / Training
California Polytechnic State University
Electrical Engineering, B.S. (September 2021 - Present)
San Luis Obispo, CAI am currently pursuing a Bachelor of Science degree in Electrical Engineering at Cal Poly, with a minor in computer science. Some of my relevant coursework includes:
- Electric Circuits I-III
- Energy Conversion Electromagnetics
- Continuous/Discrete Time Signals & Systems
- Probability & Random Processes
- Electromagnetic Fields & Transmission
- Physics I-III
- Modern Physics
- Data Structures
- Object Oriented Programming
- Digital Design and Assembly Programming
- Semiconductor Device Electronics
- Microprocessor System Design
- Computer Hardware Architecture & Design
- Classical Control Systems
- Analog Electronics & Integrated Circuits
- Digital Signal Processing
- Microcontroller-Based Systems Design
- Vision-Based Robotic Manipulation and Lab
- Power Electronics & Lab